ASIX ELECTRONICS CORPORATION

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AX88195 Local CPU Bus Fast Ethernet MAC Controller

Appendix C: Application Note for RDY is not applicable

This application note is for some kind of CPU that doesn’t support asynchronous wait state insertion function.

For example, 8051 CPU series have only fix access cycle time. For some application that the CPU has the

capability of wait state insertion, but the designer do not want to use the handshake signal in order to simply the

design. This application note is helpful for those cases.

The following criteria must be meet:

1. The bus access timing must meet the AC timing specification.

2. The “remote DMA” move data from/to data port access time can’t faster than 120ns.

Solution:

Because of the access time from FIFO to Packet Buffer RAM or from Packet Buffer RAM to FIFO is

120ns/Word. The “remote DMA read” operation is the only case that RDY signal will be active to request some

wait state to pre-fetch data from RAM into FIFO. As soon as the first word of data feed into the FIFO, the RDY

will not active again for the lasting cycle. For the critical time, just insert “No Operation” instruction (to insert

wait state using software) after write remote DMA read command and before read data port.

Ex : IOBASE=300 ; Insert wait state by software.

Mov dx,308h

; Index = 308h

Mov al,0h

;

Out dx,al

; Set Remote Start Address low byte = 0

Inc

dx

; Index = 309h

Mov al,4dh

;

Out dx,al

; Set Remote Start Address high byte = 4d

Inc

dx

; Index = 30Ah

Mov al,40h

;

Out dx,al

; Set Remote DMA Byte Count low byte = 40h

Inc

dx

; Index = 30Bh

Mov al,40h

;

Out dx,al

; Set Remote DMA Byte Count high byte = 00h

Mov dx,300h

; Index = 300h

Mov al,0ah

;

Out dx,al

; Set remote DMA read command

Nop

; Insert wait state here

Nop

; Insert more wait states again if necessary

Mov dx,310h

; Index = 310h

Lea

di, RxBuffer

; Set Rx Buffer Address

Mov cx, RxLen

; Set Rx Length

Rep insw

; Read data port

…