STM32W108CB datasheet(132/278 Pages) STMICROELECTRONICS

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Serial interfaces

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

9.9.2

Serial controller SPI control register (SCx_SPICR)

Address offset: 0xC858 (SC1_SPICR) and 0xC058 (SC2_SPICR)

Reset value:

0x0000 0000

Reserved, must be kept at reset value

RXMODE: Receiver-driven mode selection bit (SPI master mode only)

MSTR: Master selection

RPTEN: Repeat enable

LSBFIRST: Frame format

CPHA: Clock phase

CPOL: Clock polarity

Reserved

MODE

MSTR

TEN

LSB

FIRST

CPHA

CPOL

Bits [31:6]

Bit 5

0: Initiate transactions when transmit data is available.

1: Initiate transactions when the receive buffer (FIFO or DMA) has space. Force immediate

transmission of busy token or resend last byte (depending on RPTEN) and receive data into

FIFO until the FIFO is full.

Bit 4

0: Slave configuration

1: Master configuration

Bit 3

This bit controls behavior on a transmit buffer underrun condition in slave mode. Clear this bit

to send the BUSY token (0xFF) and set this bit to repeat the last byte. Changes to this bit take

effect when the transmit FIFO is empty and the transmit serializer is idle.

Bit 2

0: Most significant bit transmitted first

1: Least significant bit transmitted first

Bit 1

0: The first clock transition is the first data capture edge

1: The second clock transition is the first data capture edge

Bit 0

0: CK to 0 when idle

1: CK to 1 when idle

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