STM32W108CB datasheet(163/278 Pages) STMICROELECTRONICS

Il numero della parte	STM32W108CB

Spiegazioni elettronici	High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory

PDF	278 Pages

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Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose timers

Doc ID 16252 Rev 14

163/278

In addition, if the URS bit in the TIMx_CR1 register is set, setting the UG bit generates an

update event, but without setting the UIF flag. Thus no interrupt request is sent. This avoids

generating both update and capture interrupt when clearing the counter on the capture

event.

When an update event occurs, the update flag (the UIF bit in the TIMx_SR register) is set

(depending on the URS bit in the TIMx_CR1 register) and the following registers are

updated:

●

The prescaler shadow register is reloaded with the buffer value (contents of the

TIMx_PSC register).

●

The auto-reload active register is updated with the buffer value (contents of the

TIMx_ARR register). If the update source is a counter overflow, the auto-reload is

updated before the counter is reloaded, so that the next period is the expected one.

The counter is loaded with the new value.

The following figures show some examples of the counter behavior for different clock

frequencies.

Figure 23.

Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

CK_INT

CNT_EN

Timer clock = CK_CNT

Counter register

Update interrupt flag (UIF)

Counter underflow

Update event (UEV)

03 04 05 06 05 04 03

03 02 01 00 01

Counter overflow

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