STM32W108CB datasheet(186/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Using one timer to enable the other timer

In this example, the enable of Timer 2 is controlled with the output compare 1 of Timer 1.

Refer to Figure 45 for connections. Timer 2 counts on the divided internal clock only when

OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the

prescaler compared to CK_INT (fCK_CNT = fCK_INT /3).

●

Configure Timer 1 in master mode to send its Output Compare Reference (OC1REF)

signal as trigger output (MMS = 100 in the TIM1_CR2 register).

●

Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).

●

Configure Timer 2 to get the input trigger from Timer 1 (TS = 000 in the TIM2_SMCR

●

Configure Timer 2 in Gated mode (SMS = 101 in the TIM2_SMCR register).

●

Enable Timer 2 by writing 1 in the CEN bit (TIM2_CR1 register).

●

Start Timer 1 by writing 1 in the CEN bit (TIM1_CR1 register).

Note:

The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2

counter enable signal.

Figure 46.

Gating Timer 2 with OC1REF of Timer 1

In the example in Figure 46, the Timer 2 counter and prescaler are not initialized before

being started. So they start counting from their current value. It is possible to start from a

given value by resetting both timers before starting Timer 1, then writing the desired value in

the timer counters. The timers can easily be reset by software using the UG bit in the

TIMx_EGR registers.

TIE

Write TIE=0

3045

3047

3048

CK_INT

TIMER1-OC1REF

TIM1-CNT

TIM2-CNT

3046

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