STM32W108CB datasheet(228/278 Pages) STMICROELECTRONICS

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Analog-to-digital converter

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

11.3.3

ADC control register (ADC_CR)

Address offset: 0xD004

Reset value:

0x0000 1800

Reserved

SMP[2:0]

HVSELP

HVSELN

CHSELP[3:0]

CHSELN[3:0]

CLK

Reserved

ADON

Bits [31:16] Reserved, must be kept at reset value

Bits [15:13] SMP[2:0]: ADC sample time in clocks and the equivalent significant bits in the conversion

0: 32 clocks (5 bits)

1: 64 clocks (6 bits)

2: 128 clocks (7 bits)

3: 256 clocks (8 bits)

4: 512 clocks (9 bits)

5: 1024 clocks (10 bits)

6: 2048 clocks (11 bits)

7: 4096 clocks (12 bits)

Bit 12 HVSELP: Select voltage range for the P input channel

0: Low voltage range (input buffer disabled)

1: High voltage range (input buffer enabled)

Bit 11 HVSELN: Select voltage range for the N input channel

0: Low voltage range (input buffer disabled).

1: High voltage range (input buffer enabled).

Note: For the STM32W108CC and STM32W108CZ, the HVSELN register allows the chopper

to be controlled.

Bits [10:7] CHSELP[3:0]: Input selection for the P channel

0x0: PB5 pin

0x1: PB6 pin

0x2: PB7 pin

0x3: PC1 pin

0x4: PA4 pin

0x5: PA5 pin

0x8: GND (0V) (not for high voltage range)

0x9: VREF/2 (0.6V)

0xA: VREF (1.2V)

0xB: VREG/2 (0.9V) (not for high voltage range)

0x6, 0x7, 0xC-0xF: Reserved, must be kept at reset value

Bits [6:3] CHSELN[3:0]: Input selection for the N channel

Refer to CHSELP[3:0] above for choices

Bit 2 CLK: Select ADC clock:

0: 6 MHz1: 1 MHz

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