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DF2S23P2FU Scheda tecnica(PDF) 2 Page - Toshiba Semiconductor

Il numero della parte DF2S23P2FU
Spiegazioni elettronici  ESD Protection Diodes Silicon Epitaxial Planar
PDF  8 Pages
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Produttore elettronici  TOSHIBA [Toshiba Semiconductor]
Homepage  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

DF2S23P2FU Scheda tecnica(HTML) 2 Page - Toshiba Semiconductor

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DF2S23P2FU
2
5.
5.
5.
5. Example of Circuit Diagram
Example of Circuit Diagram
Example of Circuit Diagram
Example of Circuit Diagram
6.
6.
6.
6. Quick Reference Data
Quick Reference Data
Quick Reference Data
Quick Reference Data
Characteristics
Working peak reverse voltage
Dynamic resistance
Electrostatic discharge voltage
(IEC61000-4-2) (Contact)
Symbol
VRWM
RDYN
VESD
Note
(Note 1)
(Note 2)
(Note 3)
Test Condition
Min
Typ.
0.13
Max
21
30
Unit
V
kV
Note 1: Recommended operating condition.
Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of
dynamic resistance using least squares fit of TLP characteristics between IPP1 = 16 A and IPP2 = 30 A.
Note 3: Criterion: No damage to devices.
6.1.
6.1.
6.1.
6.1. ESD Clamp Waveform (Note)
ESD Clamp Waveform (Note)
ESD Clamp Waveform (Note)
ESD Clamp Waveform (Note)
Fig.
Fig.
Fig.
Fig. 6.1.1
6.1.1
6.1.1
6.1.1 +8 kV
+8 kV
+8 kV
+8 kV
Fig.
Fig.
Fig.
Fig. 6.1.2
6.1.2
6.1.2
6.1.2 -8 kV
-8 kV
-8 kV
-8 kV
Fig.
Fig.
Fig.
Fig. 6.1.3
6.1.3
6.1.3
6.1.3 IEC61000-4-2 (Contact)
IEC61000-4-2 (Contact)
IEC61000-4-2 (Contact)
IEC61000-4-2 (Contact)
Note:
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
2018-08-07
Rev.2.0
©2017-2018
Toshiba Electronic Devices & Storage Corporation



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