GreenSIDE - STW51000

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Overview/Description

GreenSIDE is a cost-effective, System-on-Chip device that targets applications in wireless infrastructure

equipment. The device combines two quad-MAC ST140 DSP cores, a standard ARM926-EJS RISC pro-

cessor core providing a total of 29000 Mops, 7500 Mips, 4800MMacs/s, 16Mb of embedded SRAM mem-

ory, dedicated Turbo Decoding Engine (TDE) for Data error correction, and Convolutional Decoding

Engine (CDE) for Voice error correction for 2.5G and 3G standards, with a complete set of high-perfor-

mance peripherals. As a highly-integrated baseband modem solution, GreenSIDE offers a unique oppor-

tunity to significantly reduce the overall cost/channel and cost/MIPS.

The GreenSIDE Super Integrated DSP Engine is based on the ST Open Wireless Infrastructure Platform.

This is an extendable solution comprising hardware, software and integration tools used to develop a cost

effective Wireless Infrastructure silicon solutions in a very short time.

The GreenSIDE ASSP is designed to be extremely flexible to suit all leading-edge wireless standards

such as W-CDMA, CDMA2000, TD-SCDMA and EDGE. GreenSIDE is a step forward in the System Inte-

gration race. It offers a true System-on-Chip solution, including multiple embedded cores, and infrastruc-

ture application specific IP elements.

Figure 2. GreenSIDE ASSP Block Diagram

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Architecture Overview

The GreenSIDE architecture is designed using ASIC Methodology. It employs re-usable embeddable

cores as well as application specific IP blocks such as a Turbo Decoder Engine, Convolution Decoder En-

gine, UTOPIA Interface, Multi-channel Serial Ports, Ethernet MAC, etc.

The GreenSIDE Super Integrated DSP Engine includes two ST140 Digital Signal Processing CPUs. Each

ST140 is a Quad-MAC DSP engine, able to process up to 24 complete W-CDMA modems for 12.2 kbps

voice users. Having two ST140 instances provides the support of 48 above defined voice users process-

ing capability.

GreenSIDE also includes an ARM926 micro-controller, used as a master for the complete system. It al-

lows the setup of peripherals within the system, and schedules the DSP task execution.

²

DMA Periph

2 x Ethernet

MAC

2x MSP

External Memory

Interface

VIC

UTOPIA

Core Periph

System

Control

PLL

2 x 32-bit

Timers

32-bit GPIO

1 x UARTs

COPRO

Convolutional

Decoder

Engine

Turbo Decoder

Engine

Parallel

Com.

Interfaces

Cross Bar

Data

Cache

Program

Cache

ETM

ST140

DSP

ITC

Timers

UART

Bus Switch

ITC

Timers

UART

Bus Switch

DMA

GMM

2 MB

(SRAM)

ARM

926

ST140

DSP