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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

Address

(hex)

Bit

Reset

value

Description

302188h

REG_SPI_WIDTH

r/w

QSPI bus width setting

Bit [2]: extra dummy cycle on read

Bit [1:0]: bus width (0=1-bit, 1=2-bit,

2=4-bit)

30218Ch

REG_TOUCH_DIRECT_XY

REG_CTOUCH_TOUCH2_XY

r/o

Compatibility mode: Touch screen direct

(x-MSB16; y-LSB16) conversions

Extended mode: touch-screen screen

data for touch 2 (x-MSB16; y-LSB16)

302190h

REG_TOUCH_DIRECT_Z1Z2

REG_CTOUCH_TOUCH3_XY

r/o

Compatibility mode: Touch screen direct

(z1-MSB16; z2-LSB16) conversions

Extended mode: touch-screen screen

data for touch 3 (x-MSB16; y-LSB16)

302194h-

302560h

Reserved

302564h

REG_DATESTAMP

128

r/o

Stamp date code

302574h

REG_CMDB_SPACE

r/w

FFCh

Command DL (bulk) space available

302578h

REG_CMDB_WRITE

w/o

Command DL (bulk) write

Table 5-2 Overview of FT81x Registers

Note: All register addresses are 4-byte aligned. The value in the “Bits” column refers to the number of

valid bits from bit 0 unless otherwise specified; other bits are reserved.

5.2 Chip ID

The FT81x Chip ID can be read at memory location 0C0000h – 0C0003h. The reset values of these bytes

are:

0C0000h: 08h

0C0001h: 10h (FT810), 11h(FT811), 12h(FT812), 13h(FT813)

0C0002h: 01h

0C0003h: 00h

Note that the Chip ID location can be over-written by software.

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