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FT900L-R Scheda tecnica(PDF) 48 Page - Bridgetek Pte Ltd. |
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FT900L-R Scheda tecnica(HTML) 48 Page - Bridgetek Pte Ltd. |
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48 / 67 page ![]() Copyright © Bridgetek Pte Ltd 48 FT900 /1/2/3 Revision C Embedded Microcontroller Datasheet Version 1.0 Document No. BRT_000172 Clearance No.: BRT#087 I2S Master I/O pins dynamic characteristics (Vcc (I/O) = 3.3V) Table 5-15 - I2S Master I/O pins (I2S_LRCLK/BCLK/SDAI/SDAO) characteristics Figure 5-9 - Definition of I2S Master Timing Parameter Description Min Typ Max Unit Conditions TD(LRCLK) LRCLK delay time 0 10 ns fs = 48kHz BCLK = 256fs TD(SDAO) SDAO delay time 0 15 ns TSU(SDAI) setup time 10 ns TH(SDAI) hold time 10 ns |
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