48LM01 datasheet(11/40 Pages) MICROCHIP

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DS20006008C-page 11

48L512/48LM01

4.2

DEVICE OPCODES

4.2.1

SERIAL OPCODE

After the device is selected by driving CS low, the first

byte sent must be the opcode that defines the

operation to be performed.

The 48L512/48LM01 utilizes an 8-bit instruction

codes are contained in Table 4-1. All instructions,

addresses, and data are transferred with the MSb first

and are initiated with a high-to-low CS transition and

completed with a low-to-high CS transition.

TABLE 4-1:

INSTRUCTION SET FOR 48L512/48LM01

4.2.2

HOLD FUNCTION

The HOLD pin is used to pause the serial

communication with the device without having to stop

or reset the clock sequence. The Hold mode, however,

does not have an effect on the internal write cycle.

Therefore, if a write cycle is in progress, asserting the

HOLD pin will not pause the operation and the write

cycle will continue until it is finished.

The Hold mode can only be entered while the CS pin is

asserted. The Hold mode is activated by asserting the

HOLD pin during the SCK low pulse. If the HOLD pin is

asserted during the SCK high pulse, then the Hold

mode will not be started until the beginning of the next

SCK low pulse. The device will remain in the Hold

mode as long as the HOLD pin and CS pin are

asserted.

While in Hold mode, the SO pin will be in a high-imped-

ance state. In addition, both the SI pin and the SCK pin

will be ignored.

end

the

Hold

mode

and

resume

serial

communication, the HOLD pin must be deasserted

during the SCK low pulse. If the HOLD pin is

deasserted during the SCK high pulse, then the Hold

mode will not end until the beginning of the next SCK

low pulse.

If the CS pin is deasserted while the HOLD pin is still

asserted, then any operation that may have been

started will be aborted and the device will reset the

WEL bit in the STATUS register back to the logic ‘0’

state.

Command

Operation Description

Opcode

Address

Bytes

Data

Bytes

Reference

Section

Write Control Commands

WREN

Set Write Enable Latch (WEL)

06h

0000 0110

5.1

WRDI

Reset Write Enable Latch (WEL)

04h

0000 0100

5.2

SRAM Commands

WRITE

Write to SRAM Array

02h

0000 0010

2/3

8.0

READ

Read from SRAM Array

03h

0000 0011

2/3

7.1

Secure

WRITE

Secure Write to SRAM Array with CRC

12h

0001 0010

2/3

64/128

10.1

Secure

READ

Secure Read from SRAM Array with CRC

13h

0001 0011

2/3

64/128

10.2

STATUS Register Commands

WRSR

Write STATUS Register (SR)

01h

0000 0001

6.5

RDSR

Read STATUS Register (SR)

05h

0000 0101

6.4

Store/Recall Commands

STORE

Store SRAM data to EEPROM array

08h

0000 1000

11.3

RECALL

Copy EEPROM data to SRAM array

09h

0000 1001

11.4

Nonvolatile User Space Commands

WRNUR

Write Nonvolatile User Space

C2h

1100 0010

016

9.1

RDNUR

Read Nonvolatile User Space

C3h

1100 0011

016

9.2

Hibernate Commands

Hibernate

Enter Hibernate Mode

B9h

1011 1001

12.0

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