48LM01-ISLASHSM datasheet(13/40 Pages) MICROCHIP

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DS20006008C-page 13

48L512/48LM01

5.0

WRITE ENABLE AND DISABLE

5.1

Write Enable Instruction (WREN)

The Write Enable Latch (WEL) bit of the STATUS

WRITE

instruction. The WEL bit is set to a logic ‘1’ by

sending

WREN

(06h)

command

the

48L512/48LM01. First, the CS pin is driven low to

select the device and then a 06h instruction is clocked

in on the SI pin. Then the CS pin is driven high. The

WEL bit will be immediately updated in the STATUS

The WEL bit will also be reset to a logic ‘0’ in the

following circumstances:

• Upon power-up as the power on default condition

is the Write Disable state (Section 6.2 "Write

Enable Latch")

• The completion of any write operation (WRITE,

WRSR)

• A write operation of any type to a memory location

or register that is protected or locked

• Executing a Write Disable (WRDI) instruction

(Section 5.2

"Write

Disable

Instruction

(WRDI)")

• A Hold abort occurs as noted in Section 4.2.2

"Hold Function" (CS deasserted while HOLD pin

is low)

FIGURE 5-1:

WREN WAVEFORM

5.2

Write Disable Instruction (WRDI)

To protect the device against inadvertent writes, the

Write Disable instruction (opcode 04h) disables all

programming modes by setting the WEL bit to a

logic ‘0’.

FIGURE 5-2:

WRDI WAVEFORM

SCK

234

567

High-Impedance

WREN Opcode

MSb

SCK

345

High-Impedance

WRDI Opcode

000

MSb

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