TDA4VE...ALZQ1 datasheet(158/251 Pages) TI

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Table 7-32. DPI Timing Conditions (continued)

PARAMETER

MIN

MAX

UNIT

OUTPUT CONDITIONS

Output load capacitance

1.5

PCB CONNECTIVITY REQUIREMENTS

td(Trace Mismatch Delay)

Propagation delay mismatch

across all traces

100

Table 7-33, Table 7-34, Figure 7-42 and Figure 7-43 assume testing over the recommended operating conditions

and electrical characteristic conditions.

Table 7-33. DPI Video Output Switching Characteristics

NO.(2)

PARAMETER

MIN

MAX

UNIT

tc(pclk)

Cycle time, VOUT(x)_PCLK

6.06

tw(pclkL)

Pulse duration, VOUT(x)_PCLK low

0.475×P(1)

tw(pclkH)

Pulse duration, VOUT(x)_PCLK high

0.475×P(1)

td(pclkV-dataV)

Delay time, VOUT(x)_PCLK transition to VOUT(x)_DATA[23:0]

transition

-0.68

1.78

td(pclkV-ctrlL)

Delay time, VOUT(x)_PCLK transition to control signals

VOUT(x)_VSYNC, VOUT(x)_HSYNC, VOUT(x)_DE falling edge

-0.68

1.78

(1)

P = output VOUT(x)_PCLK period in ns.

(2)

x in VOUT(x) = 1 or 2

VOUT(x)_PCLK

VOUT(x)_VSYNC

VOUT(x)_HSYNC

VOUT(x)_DATA[23:0]

VOUT(x)_DE

data_1 data_2

data_n

DPI_TIMING_01

VOUT

_PCLK

(x)

Falling-edge Clock Reference

Rising-edge Clock Reference

The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.

The polarity and the pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS)

section in Peripherals chapter in the device TRM.

The VOUT(x)_PCLK frequency can be configured, refer to Display Subsystem section in Peripherals chapter in the device TRM.

x in VOUT(x) = 1 or 2.

Figure 7-42. DPI Video Output

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

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