IC89C52(51)A

Integrated CircuitSolution Inc.

7

MC008-0C 11/27/2001

Figure 5. Programming Interface

Programming the IC89C52(51)A:

The IC89C52(51)A is normally shipped the on-chip

Flash memory array in the erased state (i.e. contents=FFH)

and ready to be programmed. The IC89C52(51)A is

programmed byte-by-byte in programming mode. Before

the on-chip flash code memory can be re-programmed, the

entire memory array must be erased electrically.

Programming Interface:

Some conditions must be satisfied before entering the

programming mode. The conditions are listed following.

1. RST is high level

2.

PSEN is low level

3. P3.6 and P3.7 is high level

The interface-controlled signals are matched these

conditions, then the IC89C52(51)A will enter received

command mode. The flash command is accepted by the

flash command decoder in command received mode. The

programming interface is listed in figure 5.

VSS

RST

PSEN

ALE/PROG

EA/VPP

P2.6

P2.7

P3.6

P3.7

XTAL1

H

L

PROG pulse

12V/H

Command Write

Output Enable

H

H

1-12MHz Clock

VCC

10K

VCC

D7-D0

P0

P1

A7-A0

P2.4-2.0

A12-A8

OPERATING DESCRIPTION

The detail description of the IC89C52(51)A included in this description are:

• Memory Map and Registers

• Timer/Counters

• Serial Interface

• Interrupt System

• Other Information

The detail information desription of the IC89C52(51)A refer to IC80C52/32 data sheet