KSZ9563RNXI-TR datasheet(134/226 Pages) MICROCHIP

134 / 226 page

KSZ9563R

DS00002419D-page 134

 2017-2018 Microchip Technology Inc.

5.2.1.14

Port Operation Control 1 Register

5.2.1.15

Port Status Register

Address:

0xN021

Port N: 1-3

Size:

8 bits

Bits

Description

Type

Default

7:2

RESERVED

0000_00b

1:0

SRP Enable (for AVB)

00 = Port is not SRP enabled

01 = Port is SRP_1 enabled

10 = Port is SRP_2 enabled

11 = RESERVED

R/W

00b

Address:

0xN030

Port N: 1-3

Size:

8 bits

Bits

Description

Type

Default

7:5

RESERVED

000

4:3

Port Speed Status

For non-PHY ports, these bits duplicate the speed setting in the XMII Port

Control 1 Register bit 6 and XMII Port Control 0 Register bit 4.

For PHY ports, these bits indicate the actual link speed, which is also

available in the PHY Control Register.

00 = 10 Mb/s

01 = 100 Mb/s

10 = 1000 Mb/s

Port Duplex Status

For non-PHY ports, this bit duplicates the duplex setting in the XMII Port

Control 0 Register bit 6.

For PHY ports, this bit indicates the actual link duplex, which is also available

in the PHY Control Register.

1 = Full duplex

0 = Half duplex

1 or -

Transmit Flow Control Enabled Status

For non-PHY ports, this bit duplicates the Tx FC enable bit 5 in the XMII Port

Control 0 Register.

For PHY ports, this bit is set only when FC is enabled (PHY Auto-Negotiation

Advertisement Register, bits 11:10), link is up and FC is established via auto-

negotiation.

1 = TX flow control is enabled

0 = Disabled

KSZ9563RNXI-TR Scheda tecnica(PDF) 134 Page - Microchip Technology

KSZ9563RNXI-TR Scheda tecnica(HTML) 134 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL