KSZ9567RTXI-TR datasheet(140/232 Pages) MICROCHIP

140 / 232 page

KSZ9567R

DS00002329D-page 140

 2017-2019 Microchip Technology Inc.

Note 5-4

The default value of this field is determined by the associated configuration strap value. Refer to

Section 3.2.1, "Configuration Straps," on page 16 for additional information.

5.2.2.2

PHY Basic Status Register

PHY register 0x01.

Collision Test

1 = Enable COL test

0 = Disable COL test

R/W

Speed Select (MSB)

This bit is ignored if auto-negotiation is enabled (bit 12 in this register).

Bits [6, 13]

11 = Reserved

10 = 1000 Mb/s

01 = 100 Mb/s

00 = 10 Mb/s

R/W

Note 5-4

5:0

RESERVED

0x00

Address:

0xN102 - 0xN103

Port N: 1-5

Size:

16 bits

Bits

Description

Type

Default

100BASE-T4

0 = PHY is not 100BASE-T4 capable

100BASE-TX Full Duplex

1 = PHY is 100BASE-TX full-duplex capable

100BASE-TX Half Duplex

1 = PHY is 100BASE-TX half-duplex capable

10 Mb/s Full Duplex

1 = PHY is 10 Mb/s full-duplex capable

10 Mb/s Half Duplex

1 = PHY is 10 Mb/s half-duplex capable

10:9

RESERVED

00b

Extended Status

1 = PHY Extended Status Register contains extended status information.

RESERVED

MF Preamble Suppression

1 = PHY will accept management frames with preamble suppressed

Auto-negotiation Complete

1 = Auto-negotiation process is complete

0 = Auto-negotiation process is not complete

Remote (Far End) Fault

1 = Remote fault condition detected

0 = No remote fault detected

Bits

Description

Type

Default

KSZ9567RTXI-TR Scheda tecnica(PDF) 140 Page - Microchip Technology

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