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74HC192D Scheda tecnica(PDF) 8 Page - NXP Semiconductors

Il numero della parte 74HC192D
Spiegazioni elettronici  Presettable synchronous BCD decade up/down counter
PDF  13 Pages
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Produttore elettronici  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HC192D Scheda tecnica(HTML) 8 Page - NXP Semiconductors

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December 1990
8
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT192
tW
up clock pulse width
HIGH or LOW
120
24
20
39
14
11
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.7
tW
down clock pulse width
HIGH or LOW
140
28
24
50
18
14
175
35
30
210
42
36
ns
2.0
4.5
6.0
Fig.7
tW
master reset pulse width
HIGH
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.10
tW
parallel load pulse width
LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.9
trem
removal time
PL to CPU, CPD
50
10
9
3
1
1
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.9
trem
removal time
MR to CPU, CPD
50
10
9
0
0
0
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.10
tsu
set-up time
Dn to PL
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.11 note:
CPU =CPD =
HIGH
th
hold time
Dn to PL
0
0
0
−14
−5
−4
0
0
0
0
0
0
ns
2.0
4.5
6.0
Fig.11
th
hold time
CPU to CPD,
CPD to CPU
80
16
14
19
7
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.13
fmax
maximum up, down clock
pulse frequency
4.0
20
24
12
36
43
3.2
16
19
2.6
13
15
MHz
2.0
4.5
6.0
Fig.7
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
−40 to +85 −40 to +125
min.
typ.
max.
min. max. min.
max.



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