LPC2880 datasheet(21/34 Pages) PHILIPS

21 / 34 page

LPC2880_LPC2888_1

Preliminary data sheet

Rev. 01 — 22 June 2006

21 of 34

Philips Semiconductors

LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

• Power-down mode.

• Measurement range 0 V to 3.3 V.

• 10-bit conversion time

≥ 2.44 µs.

• Single or continuous conversion mode.

6.16 Analog I/O

The analog I/O system includes an I2S input channel, an I2S output channel, a dual A/D

converter, and a dual D/A converter. Each channel includes a separate 4 sample FIFO.

Each of the two ADC inputs includes a Programmable Gain Ampliﬁer (PGA). A separate

input, which can be routed to either ADC, also include an additional Low Noise Ampliﬁer

(LNA).

Each DAC has associated pins for unbuffered and ampliﬁed outputs.

6.16.1 Features

• I2S-bus input channel with a 4 sample FIFO for stereo Digital Analog Input (DAI).

• I2S-bus output channel with a 4 sample FIFO for stereo Digital Analog Output (DAO).

• Dual 16-bit A/D converters with individual inputs routed through programmable gain

ampliﬁers. Each ADC can alternatively take its input from a single pin that includes an

additional low noise ampliﬁer. Input takes place through a 4 sample FIFO.

• Dual 16-bit D/A converters. Each DAC includes both a direct output and an ampliﬁed

output. Output takes place through a 4 sample FIFO.

6.17 USB 2.0 high-speed device controller

The USB is a 4 wire bus that supports communication between a host and a number (127

max.) of peripherals. The host controller allocates the USB bandwidth to attached devices

through a token based protocol. The bus supports hot plugging, un-plugging and dynamic

conﬁguration of the devices. All transactions are initiated by the host controller.

The host schedules transactions in 1 ms frames. Each frame contains an SoF marker and

transactions that transfer data to/from device endpoints. Each device can have a

maximum of 16 logical or 32 physical endpoints. There are 4 types of transfers deﬁned for

the endpoints. Control transfers are used to conﬁgure the device. Interrupt transfers are

used for periodic data transfer. Bulk transfers are used when rate of transfer is not critical.

Isochronous transfers have guaranteed delivery time but no error correction.

The LPC2880/LPC2888 USB controller enables 480 Mbit/s or 12 Mbit/s data exchange

with a USB host controller. It includes a USB controller, a DMA engine, and a USB 2.0

ATX physical interface.

The USB controller consists of the protocol engine and buffer management blocks. It

includes an SRAM that is accessible to the DMA engine and to the processor via the

The DMA engine is an AHB master, having direct access to all ARM memory space but

particularly to on-chip RAM. Each USB endpoint that requires its data to be transferred via

DMA is allocated to a logical DMA channel in the DMA engine.

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