74LVC06AD datasheet(2/16 Pages) PHILIPS

2 / 16 page

2000 Mar 07

Philips Semiconductors

Product speciﬁcation

Hex inverter with open-drain outputs

74LVC06A

FEATURES

• 5 V tolerant inputs and outputs (open drain) for

interfacing with 5 V logic

• Wide supply voltage range from 1.65 to 5.5 V

• CMOS low power consumption

• Direct interface with TTL levels

• Inputs accept voltages up to 5 V

• Complies with JEDEC standard no. 8-1A.

DESCRIPTION

The 74LVC06A is a high-performance, low-power,

low-voltage, Si-gate CMOS device, superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. This

feature allows the use of these devices as translators in a

mixed 3.3 to 5 V environment.

The 74LVC06A provides six inverting buffers.

The outputs of the 74LVC06A devices are open drain and

can be connected to other open-drain outputs to

implement active-LOW wired-OR or active-HIGH

wired-AND functions.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.

Note

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

Σ(CL × VCC2 × fo) = sum of the outputs.

FUNCTION TABLE

See note 1.

Note

1. H = HIGH voltage level;

L = LOW voltage level;

Z = high impedance OFF-state.

SYMBOL

PARAMETER

CONDITIONS

TYP.

UNIT

tPLZ/tPZL

propagation delay nA to nY

CL = 50 pF; VCC = 3.3 V

2.3

input capacitance

5.0

CPD

power dissipation capacitance per gate

VI = GND to VCC; note 1

8.0

INPUT

OUTPUT

74LVC06AD Scheda tecnica(PDF) 2 Page - NXP Semiconductors

74LVC06AD Scheda tecnica(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Scheda tecnica Scarica

Link URL