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CS1311 Scheda tecnica(PDF) 21 Page - National Semiconductor (TI) |
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CS1311 Scheda tecnica(HTML) 21 Page - National Semiconductor (TI) |
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21 / 25 page ![]() Revision 2.2 21 www.national.com Signal Definitions (Continued) 2.2.12 Power, Ground, and No Connections Signal Name Ball No. Type Description VDDQ K20 PWR Quiet VDD for the PLL Subsystem. Should be supplied from VDD through a low-Q series inductor. It should be bypassed for AC to VSSQ, using a dual capacitor bypass (high and low frequency AC bypass). VSSQ L19 GND Quiet VSS for the PLL Subsystem. ShouldbeAC bypassed toVDDQ, otherwise left DC floating. It is connected on-chip to VSS.Noexternal coil or other connection to board ground is needed; such a connection would create a ground loop. VDD See Table 2-3 on page 12 PWR 2.5V CS1301 Core Power Connection (Total of 24). 2.2V CS1311 Core Power Connection (Total of 24). VCC See Table 2-3 on page 12 PWR 3.3V I/O Power Connection (Total of 24). VSS See Table 2-3 on page 12 GND Ground Connection (Total of 50). NC A9, A10, A11, B9, B10, B11, E19, D19 --- No Connection. For normal operation, leave unconnected. |
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