STM32H7B0IB datasheet(194/205 Pages) STMICROELECTRONICS

194 / 205 page

Date

Revision

Changes

Updated Table 66. Output timing characteristics (HSLV OFF) and

Table 67. Output timing characteristics (HSLV ON).

Updated Table 60. ESD absolute maximum ratings.

Added notes related to performance degradation at VOS1 in Section 6.3.18 FMC

characteristics, Section 6.3.19 Octo-SPI interface characteristics,

Section 6.3.32 PSSI interface characteristics, Section 6.3.33 LCD-

TFT controller (LTDC) characteristics, Section 6.3.36.2 USART

interface characteristics, Section 6.3.36.3 SPI interface characteristics,

Section 6.3.36.4 I2S Interface characteristics, Section 6.3.36.5 SAI

characteristics, Section 6.3.36.6 MDIO characteristics, Section 6.3.36.7 SD/

SDIO MMC card host interface (SDMMC) characteristics, Section 6.3.36.9 USB

OTG_HS characteristics and Section 6.3.36.10 JTAG/SWD interface

characteristics. Updated F(CLK) measurement conditions in Table 88. OCTOSPI

characteristics in SDR mode and Table 89. OCTOSPI characteristics in DTR

mode (with DQS)/Octal and Hyperbus.

Added Figure 45. ADC conversion timing diagram.

Added Section 6.3.32 PSSI interface characteristics.

Updated Figure 57. USART timing diagram in Master mode and

Figure 58. USART timing diagram in Slave mode.

Added note related to ULPI transceivers operating at 1.8 V in

Table 123. Dynamics characteristics: USB ULPI.

16-Sep-2020

Updated VDDMMC separate supply pad in Section 2 Description.

In Section 3.31 True random number generator (RNG), changed "random

number generator" in "true random number generator" and description updated.

Updated Figure 12. Power supply scheme and Section 6.3.2 VCAP external

capacitor.

Added VBAT in Section 6.3.1 General operating conditions.

Updated High-speed external user clock generated from an external source and

Low-speed external user clock generated from an external source.

Added reference to application note AN4899 in Section 6.3.16 I/O port

characteristics.

Updated DuCyCKOUT in Table 106. DFSDM measured timing 1.62-3.6 V

Updated and .

28-Sep-2020

Updated VHSEL maximum value in Table 45. High-speed external user clock

characteristics.

04-May-2021

Added indication that patents apply to the devices in Section Features.

Added reference to errata sheet in Section 1 Introduction.

Updated WKUP signals in Figure 1. STM32H7B0xB block diagram and in

Table 7. STM32H7B0xB pin/ball definition.

Updated Section 3.40 Serial peripheral interfaces (SPI)/integrated interchip

sound interfaces (I2S).

Added note to TRIM parameter in Table 50. HSI oscillator characteristics.

Extended Figure 46. ADC accuracy characteristics to both ADC resolutions and

updated Figure 47. Typical connection diagram using the ADC with FT/TT pins

featuring analog switch function.

Replace 110 °C by 130 °C in Table 98. Analog temperature sensor calibration

values.

Updated tsu(ADV-CLKH), th(CLKH-ADV), tsu(NWAIT-CLKH) and th(CLKH-NWAIT) minimum

values in Table 9. Updated tsu(DV-CLKH), th(CLKH-DV), t(NWAIT-CLKH) and th(CLKH-

NWAIT) minimum values in Table 80. Synchronous non-multiplexed NOR/PSRAM

read timings. Updated tsu(SDCLKH _Data) and th(SDCLKH _Data) minimum values in

Table 84. SDRAM read timings. Updated tsu(SDCLKH_Data) and th(SDCLKH_Data)

minimum values in Table 85. LPSDR SDRAM read timings.

STM32H7B0xB

DS13196 - Rev 7

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