4.5

SPI characteristics

The SPI latency for the product is 2 bytes.

Table 9. SPI electrical characteristics

Data based on design simulation and/or characterization results, not tested in production.

Symbol

Parameter

Min.

Max. Unit

fSCK

SPI clock frequency with max baud rate (f/2)

-

34

MHz

tc(SCK)

1/fSCK

29.4

-

ns

tsu(SI)

Data input setup time

5

-

ns

th(SI)

Data input hold time

5

-

tv(SO)

Data output valid time

13

th(SO)

Data output hold time

0

-

tSU(NSS) Setup time

5 + 0.5 × tC (SPI_CLK)

-

th(NSS)

Hold time

5 + 0.5 × tC (SPI_CLK)

-

tdis(SO)(1) Data output disable time

2

10

ns

ta(SO)(2) Data output access time

0

25

ns

tdelay

Minimum delay time between SPI_CLK going low and SPI_NSS going low

7

-

ns

1. The Min. time is the minimum time required to invalidate the data output; the Max. time is the maximum time required for the

data output to go to high impedance.

2. The Min. time is the minimum time required to drive the data output; the Max. time is the maximum time required to validate

the data output.

Figure 7. SPI slave timing diagram - SPI_CLK low (by default)

CPHA=0

SPI_MOSI

input

SPI_MISO

output

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

CPOL=0

BIT1 IN

SPI_NSS input

tSU(NSS)

tc(SCK)

th(NSS)

ta(SO)

tw(SCKH)

tv(SO)

th(SO)

tdis(SO)

tsu(SI)

th(SI)

ST33TPHF2XSPI

SPI characteristics

DS14186 - Rev 1

page 14/35