Rev C 1/5/15

10

LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK

85408 DATA SHEET

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both signals must meet the VPP and VCMR

input requirements. Figures 2A to 2F show interface examples for the

HiPerClockS CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 2A, the input

termination applies for IDT HiPerClockS open emitter LVHSTL

drivers. If you are using an LVHSTL driver from another vendor, use

their termination recommendation.

2A. HiPerClockS CLK/nCLK Input Driven by an IDT

Open Emitter HiPerClockS LVHSTL Driver

Figure 3C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2E. HiPerClockS CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 2B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

Figure 2F. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

R1

50

Ω

R2

50

Ω

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

HCSL

*R3

*R4

CLK

nCLK

3.3V

3.3V

Differential

Input

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

R1

120

Ω

R2

120

Ω

R3

120

Ω

R4

120

Ω