STLC8201

2/5

an advanced DMA engine that delivers packet prioritization.

The chip comprises three major blocks:

-Front End -Interface to the radio and PA

-Modem - OFDM and CCK digital signal processing for RX and TX

-MAC -CPU, protocol accelerator, memory, host and peripheral interfaces.

The flexible Front-End RF interface provides baseband I/Q receive inputs and transmit outputs along with

a general purpose serial interface for configuration and testing of the STLC8100 and PA module. The host

interface supports mini-PCI and CardBus32.

A powerful CPU is supported by the hardware accelerator that carries out the real time tasks of interpreting

received packets then preparing and responding fast enough to deliver sustained 54MBits/sec throughput

without losing the flexibility to future-proof the design. The embedded DMA engine increases efficiency by

rapidly sorting data as it passes through the system without loading the processor core.

Ample on-chip memory is provided to run all MAC software with sufficient space capacity to accommodate

future enhancements avoiding the need for external flash. A serial EEPROM memory interface is provided

on which the PCI/CardBus configuration and MAC address is stored.

Figure 2. Block Diagram

Modem

Logic

Front

End

DAC

Hardware

Accelerator

ADC

CPU

System

Memory

Host

Interface

STLC8201

Host

PC

STLC8100

Modem

Logic

Front

End

DAC

Hardware

Accelerator

ADC

CPU

System

Memory

Host

Interface

STLC8201

Host

PC

STLC8100