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AD7142

Rev. 0 | Page 27 of 68

GPIO INT OUTPUT CONTROL

The INT output signal can be controlled by the GPIO pin when

the GPIO is configured as an input. The GPIO is configured as

an input by setting the GPIO_SETUP bits in the interrupt

configuration register to 01. See the GPIO section for more

information on how to configure the GPIO.

Enable the GPIO interrupt by setting the GPIO_INT_EN bit in

bit to 0. The GPIO status bit in the conversion complete interrupt

status register reflects the status of the GPIO interrupt. This bit is

set to 1 when the GPIO has triggered INT. The bit is cleared on

readback from the register, provided the condition that caused

the interrupt has gone away.

The GPIO interrupt can be set to trigger on a rising edge, falling

edge, high level, or low level at the GPIO input pin. Table 14

shows how the settings of the GPIO_INPUT_CONFIG bits in

the interrupt enable register affect the behavior of INT.

Figure 38 to Figure 41 show how the interrupt output is cleared

on a read from the CDC conversion complete interrupt status

GPIO

INPUT

INT

OUTPUT

SERIAL

READBACK

GPIO

INPUT

INT

OUTPUT

NOTES

1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.

GPIO INPUT HIGH WHEN REGISTER IS READ BACK

GPIO INPUT LOW WHEN REGISTER IS READ BACK

Figure 38. INT Output Controlled by the GPIO Input Example,

GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00

GPIO

INPUT

INT

OUTPUT

SERIAL

READBACK

GPIO

INPUT

INT

OUTPUT

GPIO INPUT HIGH WHEN REGISTER IS READ BACK

GPIO INPUT LOW WHEN REGISTER IS READ BACK

NOTES

1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.

Figure 39. INT Output Controlled by the GPIO Input Example,

GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01

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