M95M02-DF datasheet(40/45 Pages) STMICROELECTRONICS

40 / 45 page

Date

Revision

Changes

Updated Section 5.1.3: Power-up conditions and Section 6: Instructions.

Added Table 2: Signals vs. bump position and updated Table 3: Write-protected block size and

footnotes of Table 8: Absolute maximum ratings.

Updated Section 10: Package information, Section 10.1: SO8N package information and Section

10.2: WLCSP package information.

Updated footnote 1 of Table 20: Ordering information scheme and added Note: on Engineering

samples.

28-Sep-2018

Updated Figure 1: Logic diagram, Figure 7: Hold condition activation, Figure 8: Write enable

(WREN) sequence, Figure 9: Write disable (WRDI) sequence, Figure 10: Read Status register

(RDSR) sequence, Figure 11: Write Status register (WRSR) sequence, Figure 13: Byte Write

(WRITE) sequence and Figure 15: Read Identification page sequence.

Updated title of Section 6.6.1: Cycling with error correction code (ECC x4) and of Section 11:

Ordering information, and Note: in it.

Updated Section 10.1: SO8N package information and Section 10.2: WLCSP8 package information.

Updated Table 11: AC measurement conditions and Table 20: Ordering information scheme.

Minor text edits across the whole document.

28-Aug-2019

Added M95M02-DF.

Updated Features, Section 1: Description and Section 11: Ordering information.

Updated Figure 1: Logic diagram.

Updated Table 15: DC characteristics.

Added Table 10: Operating conditions (M95M02-DF, device grade 5).

Minor text edits across the whole document.

‑Oct‑2022

Updated:

•

Features

•

Section 2 Block diagram

•

Section 4 Connecting to the SPI bus

•

Table 16. SO8N – Mechanical data

•

Section 11 Ordering information

Minor text edits across the whole document.

M95M02-DR M95M02-DF

DS7024 - Rev 13

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