SN250QT datasheet(61/130 Pages) STMICROELECTRONICS

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SN250

Functional description—application modules

61/130

SC1_DMASTAT [0x4496]

0-R

SC1_

RXFRMB

SC1_

RXFRMA

SC1_

RXPARB

SC1_

RXPARA

SC_RXOVFB

SC_RXOVFA

SC_TXACTB

SC_TXACTA

SC_RXACTB

SC_RXACTA

0-R

SC1_RXFRMB

[9]

This bit is set when DMA receive buffer B was passed a frame error from the lower

hardware FIFO. This bit is autocleared the next time buffer B is loaded or when the

receive DMA is reset.

SC1_RXFRMA

[8]

This bit is set when DMA receive buffer A was passed a frame error from the lower

hardware FIFO. This bit is autocleared the next time buffer A is loaded or when the

receive DMA is reset.

SC1_RXPARB

[7]

This bit is set when DMA receive buffer B was passed a parity error from the lower

hardware FIFO. This bit is autocleared the next time buffer B is loaded or when the

receive DMA is reset.

SC1_RXPARA

[6]

This bit is set when DMA receive buffer A was passed a parity error from the lower

hardware FIFO. This bit is autocleared the next time buffer A is loaded or when the

receive DMA is reset.

SC_RXOVFB

[5]

This bit is set when DMA receive buffer B was passed an overrun error from the lower

hardware FIFO. Neither receive buffers were capable of accepting any more bytes

(unloaded), and the FIFO filled up. Buffer B was the next buffer to load, and when it

drained the FIFO, the overrun error was passed up to the DMA and flagged with this

bit. This bit is autocleared the next time buffer B is loaded or when the receive DMA is

reset.

SC_RXOVFA

[4]

This bit is set when DMA receive buffer A was passed an overrun error from the lower

hardware FIFO. Neither receive buffers were capable of accepting any more bytes

(unloaded), and the FIFO filled up. Buffer A was the next buffer to load, and when it

drained the FIFO the overrun error was passed up to the DMA and flagged with this

bit. This bit is autocleared the next time buffer A is loaded or when the receive DMA is

reset.

SC_TXACTB

[3]

This bit is set when DMA transmit buffer B is currently active.

SC_TXACTA

[2]

This bit is set when DMA transmit buffer A is currently active.

SC_RXACTB

[1]

This bit is set when DMA receive buffer B is currently active.

SC_RXACTA

[0]

This bit is set when DMA receive buffer A is currently active.

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