ICS8413S08I datasheet(21/35 Pages) RENESAS

Il numero della parte	ICS8413S08I

Spiegazioni elettronici	Clock Generator for Cavium Processors

PDF	35 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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October 3, 2016

8413S08 Data Sheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50



transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 4A and 4B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 4A. 3.3V LVPECL Output Termination

Figure 4B. 3.3V LVPECL Output Termination

ICS8413S08I Scheda tecnica(PDF) 21 Page - Renesas Technology Corp