MPC9331 REVISION 7 March 11, 2016

7

©2016 Integrated Device Technology, Inc.

MPC9331 Data Sheet

3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR

APPLICATIONS INFORMATION

Output Power Down (PWR_DN) Timing Diagram

Output Clock Stop (CLK_STOP) Timing Diagram

Programming the MPC9331

The MPC9331 supports output clock frequencies from

16.67 to 240 MHz. Different feedback and output divider

configurations can be used to achieve the desired input to

output frequency relationship. The feedback frequency and

divider should be used to situate the VCO in the frequency

lock range between 200 and 480 MHz for stable and optimal

operation. The FSELA, FSELB, FSELC and PWR_DN pins

select the desired output clock frequencies. Possible

frequency ratios of the reference clock input to the outputs

are 4:1, 3:1, 2:1, 1:1, 1:2, 2:3 and 3:2. Table 8 illustrates the

various output configurations and frequency ratios supported

by the MPC9331. See also Table 9 and Table 10 for further

reference.

VCO

2

VCO

4

PWR_DWN

QAx (

2)

QBx (

4)

QCx (

6)

QAx (

2)

QBx (

4)

QCx (

6)

CLK_STOP0

CLK_STOP1

QAx (

2)

QBx (

4)

QCx (

6)