HC05RC16GRSSLASHD datasheet(67/122 Pages) NXP

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MC68HC05RC16 — Rev. 3.0

General Release Specification

Carrier Modulator Transmitter (CMT)

General Release Specification — MC68HC05RC16

Section 9. Carrier Modulator Transmitter (CMT)

9.1 Contents

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

9.3

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

9.4

Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

9.4.1

Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

9.4.2

Carrier Generator Data Registers (CHR1, CLR1,

CHR2, and CLR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

9.5

Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

9.5.1

Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

9.5.2

FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

9.5.3

Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .78

9.5.3.1

End Of Cycle (EOC) Interrupt . . . . . . . . . . . . . . . . . . . . .79

9.5.3.2

Modulator Control and Status Register (MCSR) . . . . . . .80

9.5.4

Modulator Period Data Registers

(MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . .83

9.2 Introduction

The carrier modulator transmitter (CMT) module provides a means to

generate the protocol timing and carrier signals for a wide variety of

encoding schemes. It incorporates hardware to off-load the critical

and/or lengthy timing requirements associated with code generation

from the CPU, releasing much of its bandwidth to handle other tasks

such as code data generation, data decompression, or keyboard

scanning. The CMT does not include dedicated hardware configurations

for specific protocols, but is intended to be sufficiently programmable in

its function to handle the timing requirements of most protocols with

minimal CPU intervention. When disabled, certain CMT registers can be

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