HC705C9AGRSSLASHD datasheet(140/157 Pages) NXP

140 / 157 page

General Release Speciﬁcation

Control Timing

MC68HC705C9A — Rev. 2.0

Electrical Specifications

Figure 12-7. Power-On Reset Timing Diagram

Figure 12-8. External Reset Timing

3FFE

4064 t

CYC

OSC1 PIN2

INTERNAL

CLOCK3

INTERNAL

DATA BUS3

3FFE

3FFF

(NOTE 1)

1. Power-on reset threshold is typically between 1 V and 2 V.

3. Internal clock, internal address bus, and internal data bus are not available externally.

NEW

PCH

NEW

PCL

2. OSC1 line is meant to represent time only, not frequency.

4. RESET outputs VOL during 4064 POR cycles.

NOTES:

RESET PIN

(NOTE 4)

INTERNAL

ADDRESS BUS3

INTERNAL

CLOCK1

INTERNAL

ADDRESS BUS1

NOTES:

INTERNAL

DATA BUS1

3FFE

3FFF

NEW PC

1. Internal clock, internal address bus, and internal data bus are not available externally.

2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.

NEW

PCH

NEW

PCL

CODE

RESET2

3FFE

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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