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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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HC705MC4GRS/D Scheda tecnica(PDF) 47 Page - NXP Semiconductors |
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HC705MC4GRS/D Scheda tecnica(HTML) 47 Page - NXP Semiconductors |
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47 / 180 page  Interrupts Hardware Interrupts General Release Specification Interrupts 4.5.3 Serial Communications Interface Interrupt Five different serial communications interface (SCI) interrupt flags that cause an SCI interrupt whenever they are set and enabled. The interrupt flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $0FF2 and $0FF3. See Section 11. Serial Communications Interface. 4.5.4 Core Timer Interrupt Two different core timer (CTIMER) interrupt flags cause a CTIMER interrupt whenever they are set and enabled. The interrupt flags and enable bits are located in the CTIMER control and status register (CTCSR). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $0FF0 and $0FF1. See Section 12. Core Timer. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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