APR3SLASHD datasheet(33/101 Pages) NXP

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DSP56001A

Host I/O (HI) Timing

MOTOROLA

DSP56001A/D, Rev. 1

2-15

39 HR/W Low Setup Time Before

HEN Assertion

0—0—

40 HR/W Low Hold Time After

HEN Deassertion

4—4—

41 HR/W High Setup Time to

HEN Assertion

0—0—

42 HR/W High Hold Time After

HEN/HACK Deassertion

4—4—

43 HA0-HA2 Setup Time Before

HEN Assertion

0—0—

44 HA0-HA2 Hold Time After

HEN Deassertion

4—4—

45 DMA HACK Assertion to

HREQ Deassertion (See Note 5)

46 DMA HACK Deassertion to

HREQ Assertion (See Notes 5, 6)

•

for DMA RXL Read

•

for DMA TXL Write

•

all other cases

tHSDL + TC +

TH + 4

tHSDL + TC +

—

tHSDL + TC +

TH + 4

tHSDL + TC +

—

47 Delay from HEN Deassertion to

HREQ Assertion for RXL Read

(See Notes 5, 6)

tHSDL + TC +

TH + 4

—tHSDL + TC +

TH + 4

—ns

48 Delay from HEN Deassertion to

HREQ Assertion for TXL Write

(See Notes 5, 6)

tHSDL + TC +

—tHSDL + TC +

—ns

49 Delay from HEN Assertion to

HREQDeassertion for RXL

Read, TXL Write (See Notes 5, 6)

Note:

Host synchronization delay (tHSDL) is the time period required for the DSP56001 to sample any

external asynchronous input signal, determine whether it is high or low, and synchronize it to the

DSP56001 internal clock.

See Host Port Considerations in the section on Design Considerations.

This timing must be adhered to only if two consecutive writes to the TXL are executed without

polling TXDE or HREQ.

This timing must be adhered to only if two consecutive reads from one of these registers are executed

without polling the corresponding status bits or HREQ.

HREQ is pulled up by a 1 k

Ω resistor.

Specifications are periodically sampled and not 100% tested.

May decrease to 0 ns for future versions.

Table 2-9

Host I/O Timing (Continued)(27/33 MHz) (Continued)

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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