AD9511SLASHPCB datasheet(31/60 Pages) AD

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AD9511

Rev. A | Page 31 of 60

Phase Frequency Detector (PFD) and Charge Pump

The PFD takes inputs from the R counter and the N counter

(N = BP + A) and produces an output proportional to the phase

and frequency difference between them. Figure 36 is a

simplified schematic. The PFD includes a programmable delay

element that controls the width of the antibacklash pulse. This

pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. Two

bits in Register 0Dh <1:0> control the width of the pulse.

CLR1

R DIVIDER

CLR2

N DIVIDER

DOWN

CHARGE

PUMP

GND

PROGRAMMABLE

DELAY

ANTIBACKLASH

PULSE WIDTH

Figure 36. PFD Simplified Schematic and Timing (In Lock)

Antibacklash Pulse

The PLL features a programmable antibacklash pulse width that

is set by the value in Register 0Dh<1:0>. The default

antibacklash pulse width is 1.3 ns (0Dh<1:0> = 00b) and

normally should not need to be changed. The antibacklash

pulse eliminates the dead zone around the phase-locked

condition and thereby reduces the potential for certain spurs

that could be impressed on the VCO signal.

STATUS Pin

The output multiplexer on the AD9511 allows access to various

signals and internal points on the chip at the STATUS pin.

Figure 37 shows a block diagram of the STATUS pin section.

The function of the STATUS pin is controlled by Register

08h<5:2>.

PLL Digital Lock Detect

The STATUS pin can display two types of PLL lock detect:

digital (DLD) and analog (ALD). Whenever digital lock detect

is desired, the STATUS pin provides a CMOS level signal, which

can be active high or active low.

The digital lock detect has one of two time windows, as selected

by Register 0Dh<5>. The default (ODh<5> = 0b) requires the

signal edges on the inputs to the PFD to be coincident within

9.5 ns to set the DLD true, which then must separate by at least

15 ns to give DLD = false.

The other setting (ODh<5> = 1b) makes these coincidence

times 3.5 ns for DLD = true and 7 ns for DLD = false.

The DLD may be disabled by writing 1 to Register 0Dh<6>.

If the signal at REFIN goes away while DLD is true, the DLD

will not necessarily indicate loss-of-lock. See the Loss of

Reference section for more information.

OFF (LOW) (DEFAULT)

DIGITAL LOCK DETECT (ACTIVE HIGH)

N DIVIDER OUTPUT

DIGITAL LOCK DETECT (ACTIVE LOW)

R DIVIDER OUTPUT

ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN)

A COUNTER OUTPUT

PRESCALER OUTPUT (NCLK)

PFD UP PULSE

PFD DOWN PULSE

LOSS OF REFERENCE (ACTIVE HIGH)

TRI-STATE

ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN)

LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH)

LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW)

LOSS OF REFERENCE (ACTIVE LOW)

PLL MUX CONTROL

08h <5:2>

SYNC DETECT ENABLE

58h <0>

SYNC

DETECT

GND

STATUS

Figure 37. STATUS Pin Circuit CLK1 Clock Input

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