ADM1178

Preliminary Technical Data

Rev. PrD | Page 6 of 16

PIN CONFIGURATIONS

1

2

3

4

ADM1178

TOP VIEW

(NOT TO SCALE)

Vcc

ADR

SDA

GATE

ON

TIMER

SENSE

ALERTB

GND

5

SCL

10

9

8

7

6

Figure 3. Pin Configurations

PIN FUNCTIONAL DESCRIPTIONS

Table 3.

Pin No.

Name

Description

1

VCC

Positive supply input pin. The operating supply voltage range is between 3.15 V to 14 V. An undervoltage

lockout (UVLO) circuit resets the ADM1178 when a low supply voltage is detected.

2

SENSE

Current sense input pin. A sense resistor between the VCC and SENSE pins sets the analog current limit. The

mV or below.

3

ON

Undervoltage input pin. Aactive high pin. An internal ON comparator has a trip threshold of 1.3 V and the

output of this comparator is used as an enable for the hotswap operation. With an external resistor divider

from VCC to GND, this pin can be used to enable the hotswap operation one a specific voltage on VCC, giving

an undervoltage function.

4

GND

Chip Ground Pin

5

TIMER

The GATE pin turns off whenever the TIMER pin is pulled beyond the upper threshold. An overvoltage

detection with an external zener can be used to force this pin high.

6

SCL

7

SDA

8

ADR

9

GATE

GATE Output Pin. This pin is the high side gate drive of an external N-channel FET. This pin is driven by the FET

drive controller which utilises a charge pump to provide a 12 µA pull-up current to charge the FET gate pin.

The FET drive controller regulates to a maximum load current (100 mV through the sense resistor) by

modulating the GATE pin.

10

ALERTB

Alert Output Pin. Active low, open drain configuration. This pin asserts when an overcurrent condition is

present.