AD9911SLASHPCB datasheet(4/44 Pages) AD

4 / 44 page

AD9911

Rev. 0 | Page 4 of 44

SPECIFICATIONS

AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS (REF_CLK

multiplier bypassed), unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REF_CLK Multiplier Bypassed

500

MHz

REF_CLK Multiplier Enabled

125

MHz

Internal VCO Output Frequency Range

VCO Gain Bit Set1

255

500

MHz

Internal VCO Output Frequency Range

VCO Gain Bit Cleared

100

160

MHz

Crystal REF_CLK Source Range

MHz

Input Power Sensitivity

−5

dBm

Measured at the pin (single-ended)

Input Voltage Bias Level

1.15

Input Capacitance

Input Impedance

1500

Duty Cycle with REF_CLK Multiplier Bypassed

Duty Cycle with REF_CLK Multiplier Enabled

CLK Mode Select (Pin 24) Logic 1 V

1.25

1.8

1.8 V digital input logic

CLK Mode Select (Pin 24) Logic 0 V

0.5

1.8 V digital input logic

DAC OUTPUT CHARACTERISTICS

Must be referenced to AVDD

Full-Scale Output Current

10 mA is set by RSET = 1.91 kΩ

Gain Error

−10

+10

%FS

Output Current Offset

μA

Differential Nonlinearity

±0.5

LSB

Integral Nonlinearity

±1.0

LSB

Output Capacitance

Voltage Compliance Range

AVDD –

0.50

AVDD +

0.50

WIDEBAND SFDR

The frequency range for wideband SFDR is

defined as dc to Nyquist

1 MHz to 20 MHz Analog Output

−65

dBc

20 MHz to 60 MHz Analog Output

−62

dBc

60 MHz to 100 MHz Analog Output

−59

dBc

100 MHz to 150 MHz Analog Output

−56

dBc

150 t MHz to 200 MHz Analog Output

−53

dBc

WIDEBAND SFDR Improvement

Spur Reduction Enabled

Programs devices on an individual basis to

enable spur reduction. See the

SpurKiller/Multitone Mode section.

60 MHz to 100 MHz Analog Output

dBc

100 MHz to 150 MHz Analog Output

dBc

150 MHz to 200 MHz Analog Output

dBc

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