DSP56721 datasheet(13/54 Pages) NXP

13 / 54 page

Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

2.6

AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8 V and a VIH

minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in

production with respect to the 50% point of the respective input signal’s transition. DSP56720/DSP56721 output levels are

measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively.

2.7

Internal Clocks

Internal clock characteristics are listed in Table 5.

2.8

External Clock Operation

The DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip

oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in Figure 9.

Automotive

• In Normal Mode

ICCI

—

242

496

• In Wait Mode

ICCW

—

125

409

• In Stop mode

ICCS

—

107

376

Input capacitance

CIN

——

Notes:

1. The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In

order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic

intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this

benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.0 V,

VDD_IO = 3.3 V at TJ = 25° C. Maximum internal supply current is measured with VCORE_VDD = 1.10 V, VIO_VDD) = 3.4 V at

TJ = 100°C.

2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed

to float).

Table 5. Internal Clocks

No.

Characteristics

Symbol

Min

Typ

Max

Unit

Condition

Comparison Frequency

Fref

—

MHz

Fref = Fin/NR

Input Clock Frequency

Fin

Max = 200 MHz

—

PLL VCO Frequency

Fvco

200

—

400

MHz

Fvco = (Fin

× NF)/NR

Output Clock Frequency[1]

• with PLL enabled

• with PLL disabled

Fout

—

200

MHz

Fout= Fvco/NO

Fout = Fin

Duty Cycle

—

Fvco=

200 MHz–400 MHz

Notes:

Fin = External frequency, NF = Multiplication Factor, NR = Predivision Factor, NO = Output Divider

Table 4. DC Electrical Characteristics (Continued)

Characteristics

Symbol

Min

Typ

Max

Unit

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