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PI74VCX16245 Scheda tecnica(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI74VCX16245 Scheda tecnica(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 7 page ![]() 1 PS8325 09/14/98 Product Description Pericom Semiconductors PI74VCX series of logic circuits are produced in the Companys advanced 0.35 micron CMOS technology, achieving industry leading speed. The PI74VCX16245 is a 16-bit bidirectional transceiver designed for asynchronous two-way communication between data buses. The direction control input pin (xDIR) determines the direction of data flow through the bidirectional transceiver. The Direction and Output Enable controls are designed to operate this device as either two independent 8-bit transceivers or one 16-bit transceiver. The output enable (OE) input, when HIGH, disables both A and B ports by placing them in HIGH Z condition. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pull-up resistor; the minimum value of the resistor is determined by the current sinking ability of the driver. The PI74VCX family is I/O Tolerant, allowing it to operate in mixed 1.8V/3.6V systems. 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Features • The PI74VCX family is designed for low voltage operation VDD=1.8Vto3.6V • 3.6V I/O Tolerant Inputs and Outputs • Supports Live Insertion • Balanced output drive, ±24mA • Uses patented Noise Reduction Circuitry • Typical VOLP (Output Ground Bounce) < 0.6V at VDD = 2.5V, TA = 25ºC • Typical VOHV (Output VOH Undershoot) < -0.6V at VDD = 2.5V, TA = 25ºC • Power-Off High Impedance inputs and outputs • Industrial operation at 40°C to +85°C • Packages available: 48-pin240mil.wideplasticTSSOP(A) 48-pin300mil.wideplasticSSOP(V) PI74VCX16245 2.5V 16-Bit Bidirectional Transceiver with 3-State Outputs Logic Block Diagram 1B0 1A0 1OE 1DIR 1B1 1A1 1B2 1A2 1B3 1A3 1B4 1A4 1B5 1 A5 1B6 1A6 1B7 1A7 2 B0 2 A0 2 OE 2 DIR 2 B1 2 A1 2 B2 2 A3 2 B3 2 A4 2 B4 2 A5 2 B5 2 A6 2 B6 2 A7 2 B7 2 A8 |
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