Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

28

Figure 15. SD_CLK and SD_CLK crossover timing

Figure 16. DDR Write Timing

8

Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line

becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other

factors).

becomes invalid.

SD_CLK

SD_CLK

SD_CLK

SD_CSn,SD_WE,

DM3/DM2

D[31:24]/D[23:16]

A[13:0]

SD_RAS, SD_CAS

CMD

ROW

DD1

DD5

DD4

COL

WD1 WD2 WD3 WD4

DD7

SD_DQS3/SD_DQS2

DD8

DD8

DD7

SD_CLK

DD3

DD2

DD6