6.42

13

70V35/34S/L (70V25/24S/L)

High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

NOTES:

1. R/W or CE or UB & LB must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load

(Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

the specified tWP.

9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. tEW must be met for either condition.

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)

R/

W

tWC

tHZ

tAW

tWR

tAS

tWP

DATAOUT

(2)

tWZ

tDW

tDH

tOW

OE

ADDRESS

DATAIN

(6)

(4)

(4)

(7)

CE or SEM

5624 drw 09

(9)

CE or SEM

(9)

(7)

(3)

5624 drw 10

tWC

tAS

tWR

tDW

tDH

ADDRESS

DATAIN

R/

W

tAW

tEW

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

(9)