TEA2017ABTSLASH2 datasheet(13/67 Pages) NXP

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NXP Semiconductors

TEA2017ABT/2

Digital configurable LLC and DCM/QR PFC controller

8.3 Modes of operation

Figure 10 shows the control curve between the output power and the voltage difference

between the high and low capacitor voltage levels.

aaa-026793

VSNSCAP control

VSNSCAP

Vhs(SNSCAP)

Pout(max)

Pt(lp)

Vls(SNSCAP)

VSNSCAP

burst mode

low-power mode

high-power mode

Figure 10. TEA2017ABT control curve

When the output power (Pout) is at its maximum, the low capacitor voltage level

(Vls(SNSCAP)) is at its minimum, and the high capacitor voltage (Vhs(SNSCAP)) is at its

maximum level. The maximum ΔVSNSCAP (Vhs(SNSCAP) − Vls(SNSCAP)), which is the divided

ΔVCr voltage, corresponds to the maximum output power.

When the output load decreases, the ΔVSNSCAP voltage decreases. As a result, the

output power decreases and the output voltage is regulated. This mode is called high-

power mode. Figure 8 shows a timing diagram of the system operating in high-power

mode.

When the output power drops to below the transition level (Pt(lp)), the system enters the

low-power mode. The Pt(lp) level can be initialized via the MTP.

To compensate for the non-switching period in low-power mode, also called hold period,

ΔVSNSCAP is initially increased at entering the low-power mode (see Section 8.3.2). In

low-power mode, the output power is regulated by adapting ΔVSNSCAP, until it reaches a

minimum. The system then enters the burst mode (see Section 8.3.3).

TEA2017ABT_2

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Product data sheet

Rev. 1.1 — 17 May 2023

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