ICS307-03

SERIALLY PROGRAMMABLE CLOCK SOURCE

SER PROG CLOCK SYNTHESIZER

IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE

7

ICS307-03

REV L 032911

Table 8. Miscellaneous Control Bits

External Components

The ICS307-03 requires a minimum number of external components for proper operation.

Decoupling Capacitors

TheICS307-03 requires 0.01

μF decoupling capacitors to be connected between each VDD pin and the Ground Plane. The

0.01

μF capacitors must be placed as close to the ICS307-03’s power pins as possible to minimize lead inductance.

Output Termination

The ICS307-03 has advanced output pads that allows the device to achieve very high speed (270 MHz) operation with single

ended clock outputs. The clock outputs on the ICS307-03 are designed to be directly connected to a 50 Ohm transmission

line without the need for any series resistors.

Crystal Selection

A parallel resonant, fundamental mode crystal with a load

(correlation) capacitance of 12 pF should be used. For

crystals with a specified load capacitance greater than 12

pF, additional crystal capacitors may be connected from

each of the pins X1 and X2 to ground as shown in the Block

Diagram on page 1. The value (in pF) of these crystal caps

should be = (CL-12)*2, where CL is the crystal load

capacitance in pF.

For a single ended clock input, connect it to X1 and leave X2 unconnected with no capacitors on either pin.

Initial Output Frequency

ICS307-03 on-chip registers are initially configured to

provide a 1x output clock on the CLK1 output, and 0.5x clock

on CLK2 and CLK3. The output frequency will be the same

as the input clock or crystal for input frequencies from 10 -

50 MHz. This is useful when the ICS307-03 needs to

provide an initial system clock at power-up.

Bit

Function

24~88

Reserved—set to 0

110

OE1—set to 1 to enable CLK1

111

OE2—set to 1 to enable CLK2

112

1 = Normal Operation, 0 = power down feedback counter, charge pump and VCO

122

Crystal Input = 1, Clock Input = 0

123

Selects source for CLK2 (see block diagram)

124

Selects source for CLK3 (see block diagram)

125

Reserved—set to 0

126

Reserved—set to 0

129

OE3—set to 1 to enable CLK3

130

Reserved—set to 0

131

Reserved—set to 0