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87354AMILF Scheda tecnica(PDF) 4 Page - Renesas Technology Corp |
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87354AMILF Scheda tecnica(HTML) 4 Page - Renesas Technology Corp |
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4 / 16 page ![]() ÷4/÷5 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR 87354 DATA SHEET 4 REVISION A 2/12/15 TABLE 5. AC CHARACTERISTICS, V CC = 3.0V TO 3.465V, V EE = 0, T A = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f CLK Clock Input Frequency 1 GHz t PD Propagation Delay; NOTE 1 CLK to Q (Dif) 1.7 2.1 ns tsk(pp) Part-to-Part Skew; NOTE 2, 3 300 ps t RR Reset Recovery Time 400 ps t PW Minimum Input Pulse Width CLK 550 ps t R / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle 48 52 % NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 4D. LVPECL DC CHARACTERISTICS, V CC = 3.0V TO 3.465V, V EE = 0, T A = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V OH Output High Voltage; NOTE 1 V CC - 1.4 V CC - 0.9 V V OL Output Low Voltage; NOTE 1 V CC - 2.0 V CC - 1.7 V V SWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 Ω to V CC - 2V. |
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