PCF5271CVM100 datasheet(48/56 Pages) FREESCALE

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MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 15 shows MII receive signal timings listed in Table 37.

Figure 15. MII Receive Signal Timing Diagram

8.10.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN,

ETXER, ETXCLK)

Table 38 lists MII transmit channel timings.

The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

ETXCLK frequency.

The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to transition from either the

rising or falling edge of ETXCLK, and the timing is the same in either case. This options allows the use

of non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Table 37. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

ERXD[3:0], ERXDV, ERXER to ERXCLK setup

—

ERXCLK to ERXD[3:0], ERXDV, ERXER hold

—

ERXCLK pulse width high

35%

65%

ERXCLK period

ERXCLK pulse width low

35%

65%

ERXCLK period

Table 38. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

ETXCLK to ETXD[3:0], ETXEN, ETXER invalid

—

ETXCLK to ETXD[3:0], ETXEN, ETXER valid

—

ETXCLK pulse width high

35%

65%

ETXCLK period

ETXCLK pulse width low

35%

65%

ETXCLK period

ERXCLK (input)

ERXD[3:0] (inputs)

ERXDV

ERXER

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