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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AM29BDS128HE8 Scheda tecnica(PDF) 60 Page - SPANSION |
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AM29BDS128HE8 Scheda tecnica(HTML) 60 Page - SPANSION |
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60 / 89 page  58 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A TA SH EE T AC CHARACTERISTICS Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 16. CLK Synchronous Burst Mode Read (rising active CLK) Notes: 1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock) Da Da + 1 Da + n OE# Data Addresses Aa AVD# RDY CLK CE#f tCES tACS tAVC tAVD tACH tOE tRACC tOEZ tCEZ tIACC tACC tBDH 7 cycles for initial access shown. Hi-Z Hi-Z Hi-Z 1 2 34 56 7 tRDYS tBACC tCR Da Da + 1 Da + n OE# Data Addresses Aa AVD# RDY CLK CE# tCES tACS tAVC tAVD tACH tOE tOEZ tCEZ tIACC tACC tBDH 4 cycles for initial access shown. tRACC Hi-Z Hi-Z Hi-Z 12 3 4 5 tRDYS tBACC tCR |
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