6

ICS93725

0606A—08/01/03

Switching Waveforms

Duty Cycle Timing

t1

t2

1.5V

1.5V

1.5V

SDRAM Buffer LH and HL Propagation Delay

INPUT

OUTPUT

t6

t7

Switching Characteristics

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Frequency

66

200

MHz

Input Clock Duty Cycle

din

40

60

%

DDR Static Phase Error

tped

-100

-50

100

ps

SDRAM Static Phase Error

tpes

-100

-20

100

ps

Not including FBOUT

to outputs

Not including FBOUT

to outputs

66MHz to 100MHz

48

52

%

101MHz to 200MHz

48

53

%

66MHz to 100MHz

48

52

%

101MHz to 200MHz

48

56

%

DDR Rise Time

trd

Measured between

0.55

0.68

0.95ns

DDR Fall Time

tfd

20% and 80% output, CL=16pF

0.63

0.911.15

ns

SDRAM Rise Time

trs

0.5

1.4

1.7

ns

SDRAM Fall Time

tfs

0.5

1.65

1.8

ns

DDR Cycle to Cycle Jitter

t(C-C)D

SEL_DDR=1,VDD=2.5V ,

CL=16pF

23

38

ps

SDRAM Cycle to Cycle Jitter

t(C-C)S

SEL_DDR=0,VDD=3.3V ,

CL=30pF

36

57

ps

1Guaranteed by design, not 100% tested in production.

2 While the pulse skew is almost constant over frequency, the duty cycle error increases at

higher frequencies. This is due to the formula: duty cycle=t2/t1, where the cycle (t1) decreases

as the frequency goes up.

200

DDR output to output Skew

Tskewd

60

ps

300

100

ps

SDRAM Duty Cycle

DC

2

VOL = 0.4V, VOH = 2.4V,

CL=30pF

DDR Duty Cycle

DC

2

SDRAM output to output Skew

Tskews