11

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MARCH 2013

NOTE:

1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.

Figure 8. Full Flag Timing

WCLKA

(WCLKB)

DA0 - DA8

(DB0 - DB8)

FFA (FFB)

WENA1

(

WENB1)

WENA2

(WENB2)

(If Applicable)

RCLKA

(RCLKB)

RENA1

(

RENB2)

QA0 - QA8

(QB0 - QB8)

OEA

(

OEB)

3034 drw 09

tSKEW1

tDS

tSKEW1

tENH

tENH

NEXT DATA READ

DATA READ

tWFF

tWFF

tWFF

tENS

tENS

DATA IN OUTPUT REGISTER

LOW

NO WRITE

NO WRITE

tA

tA

tENS

tENS

tENS

(1)

tENS

(1)

tENH

tENH

NO WRITE

tDH

tDS

tDS

tENS

tENH

tENS

tENH

tENS

tENH

tENS

tENH

DATA WRITE 2

WCLKA (WCLKB)

DA0 - DA8

(DB0 - DB8)

RCLKA (RLCKB)

EFA (EFB)

RENA1, RENA2

(

RENB1, RENB2)

DATA READ

tSKEW1

tFRL

tFRL

(1)

tSKEW1

WENA2 (WENB2)

(If Applicable)

tREF

tREF

WENA1, (WENB1)

3034 drw 10

DATA WRITE 1

tREF

(1)

LOW

OEA (OEB)

QA0-QA8

(QB0-QB8)

DATA IN OUTPUT REGISTER

tA

NOTE:

1. When tSKEW1

≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1

< minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).

Figure 9. Empty Flag Timing