DSPIC30F datasheet(23/220 Pages) MICROCHIP

23 / 220 page

 2004 Microchip Technology Inc.

Preliminary

DS70116C-page 21

dsPIC30F5011/5013

3.0

MEMORY ORGANIZATION

3.1

Program Address Space

The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the 23-bit

PC, table instruction Effective Address (EA), or data

space EA, when program space is mapped into data

space as defined by Table 3-1. Note that the program

space address is incremented by two between succes-

sive program words in order to provide compatibility

with data space addressing.

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) for all accesses other than TBLRD/TBLWT,

which use TBLPAG<7> to determine user or configura-

tion space access. In Table 3-1, Program Space

Address Construction, bit 23 allows access to the

Device ID, the User ID and the configuration bits.

Otherwise, bit 23 is always clear.

FIGURE 3-1:

PROGRAM SPACE

MEMORY MAP

Reset - Target Address

000000

00007E

000002

000080

Device Configuration

User Flash

Program Memory

00B000

00AFFE

Data EEPROM

(22K instructions)

(1 Kbyte)

800000

F80000

Registers

F8000E

F80010

DEVID (2)

FEFFFE

FF0000

FFFFFE

Reserved

F7FFFE

Reserved

7FFC00

7FFBFE

(Read ‘0’s)

8005FE

800600

UNITID (32 instr.)

Vector Tables

8005BE

8005C0

Reset - GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Alternate Vector Table

Reserved

Interrupt Vector Table

DSPIC30F Scheda tecnica(PDF) 23 Page - Microchip Technology

DSPIC30F Scheda tecnica(HTML) 23 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL