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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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P25Q16SL Scheda tecnica(PDF) 10 Page - Puya Semiconductor Co., Ltd. |
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P25Q16SL Scheda tecnica(HTML) 10 Page - Puya Semiconductor Co., Ltd. |
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10 / 110 page  P25Q16SL Datasheet Puya Semiconductor Page 10 of 110 5.3 AC Characteristics Table 5-3-1 AC parameters(Ta=-40°C to +85°C) Symbol Alt. Parameter 1.65V~2.0V min. max. Unit fSCLK fC Clock Frequency for the following instructions except for special marking D.C. 85 MHz fRSCLK fR Clock Frequency for READ instructions 33 MHz fTSCLK fT Clock Frequency for 2READ,DREAD instructions 85 MHz fQ Clock Frequency for 4READ, QREAD, QPI 0Bh, QPI EBh, QPI 0Ch instructions 85 MHz Clock Frequency for WREAD instructions 70 MHz fD Clock Frequency for DTR instructions 43 MHz fQPP Clock Frequency for QPP (Quad page program) 85 MHz tCH(1) tCLH Clock High Time 5.5 ns tCL(1) tCLL Clock Low Time (fSCLK) 45% x (1fSCLK) 5.5 ns tCLCH(7) Clock Rise Time (peak to peak) 0.1 v/ns tCHCL(7) Clock Fall Time (peak to peak) 0.1 v/ns tSLCH tCSS CS# Active Setup Time (relative to SCLK) 5 ns tCHSL CS# Not Active Hold Time (relative to SCLK) 5 ns tDVCH tDSU Data In Setup Time 2 ns tCHDX tDH Data In Hold Time 3 ns tCHSH CS# Active Hold Time (relative to SCLK) 5 ns tSHCH CS# Not Active Setup Time (relative to SCLK) 5 ns tSHSL tCSH CS# Deselect Time From Read to next Read 20 ns CS# Deselect Time From Write, Erase, Program to Read Status Register 30 ns tSHQZ(7) tDIS Output Disable Time 6 ns tCLQV tV Clock Low to Output Valid Loading 30pF 7 ns Clock Low to Output Valid Loading 15pF 6 ns tCLQX tHO Output Hold Time 0 ns tHLCH HOLD# Active Setup Time (relative to SCLK) 5 ns tCHHH HOLD# Active Hold Time (relative to SCLK) 5 ns tHHCH HOLD# Not Active Setup Time (relative to SCLK) 5 ns tCHHL HOLD# Not Active Hold Time (relative to SCLK) 5 ns tHHQX tLZ HOLD# to Output Low-Z 6 ns tHLQZ tHZ HOLD# to Output High-Z 6 ns tWHSL(3) Write Protect Setup Time 20 ns tSHWL(3) Write Protect Hold Time 100 ns tDP CS# High to Deep Power-down Mode 3 us tRES1 CS# High To Standby Mode Without Electronic Signature Read 8 us tRES2 CS# High To Standby Mode With Electronic Signature Read 8 us tW Write Status Register Cycle Time 8 12 ms tReady Reset recovery time(for erase/program operation except WRSR) 30 us Reset recovery time(for WRSR operation) 12 8 ms tBL Load memory page data to buffer time(256Byte) 60 us Load memory page data to buffer time(512Byte) 120 us tBC Buffer clear to next instruction latency 300 ns |
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