MP8830

9

Rev. 1.00

Pass Through Mode

1.

AENL, BENL & CENL should be held high during pass-through mode. ADCs and DACs will not work properly during pass-through.

2.

Pass-through mode enable. When CREN is high, pass-through mode between the ADC and DAC ports is enabled. RNW controls the direction

of pass-through operation.

3.

READ not WRITE signal. RNW controls the direction of the pass-through operation when CREN is high, and has no impact when CREN is low.

When RNW is high, data passes from the DAC port to the ADC port. When RNW is low, data passes from the ADC port to the DAC port. Note the

port connections are: CD5; AD0; CD6; AD1;...;CD14; AD9.

Figure 4. Timing for Pass Through Mode Operation

External circuits must stop

driving CD (5-14) when RNW falls

and CREN is high

CREN

RNW

CD

(5-14)

AD

(0-9)

Chip stops

driving AD (0-9)

External circuit can

start driving AD (0-9)

Note: external circuits must stop

driving AD(0–9) when CREN falls

Chip drives AD(0-9)

data from last conversion

External circuits can

start driving CD (5-14)

CREN

RNW

CD

(5-14)

External circuits must stop

driving CD (5-14) when CREN rises

and RNW is low

Chip stops

driving AD (0-9)

External circuits can

start driving AD(0-9)

External circuits must

stop driving AD (0-9)

Chip stops driving CD(5-14)

External circuits can

start driving CD(5-14)

Pass through delay from CD(5-14) to AD(0-9)

Pass through delay from AD(0-9) to CD(5-14)

T17

Pass through set up time

Chip drives AD(0-9)

data from last conversion

AD

(0-9)