7

ICSSSTVA16859C

1114A—05/26/05

Timing Requirements

1

(over recommended operating free-air temperature range, unless otherwise noted)

MIN

MAX

fclock

Clock frequency

270

MHz

tSL

Output slew rate

1

4

V/ns

Setup time, fast slew rate

2 & 4

0.4

ns

Setup time, slow slew rate

3 & 4

0.6

ns

Hold time, fast slew rate

2 & 4

0.4

ns

Hold time, slow slew rate

3 & 4

0.5

ns

1 - Guaranteed by design, not 100% tested in production.

2 - For data signal input slew rate of ≥ 1V/ns.

4 - CLK, CLK# signals input slew rate of ≥ 1V/ns.

SYMBOL

tS

Th

Notes:

3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns.

VDDQ = 2.5V ± 0.2V

UNITS

PARAMETERS

Data before CLK↑ , CLK#↓

Data after CLK↑ , CLK#↓

Switching Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)

(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)

MIN

TYP

MAX

fmax

210

MHz

CLK, CLK# (TSSOP)

Q

1.6

2.1

2.6

ns

CLK, CLK# (VFQFN[MLF2])

Q

1.6

2.1

2.6

ns

tphl

RESET#

Q

3.5

ns

SYMBOL

VDD = 2.5V ±0.2V

UNITS

From

(Input)

To

(Output)

tPD

Switching Characteristics - DDRI-400 (PC3200)

(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)

MIN

TYP

MAX

fmax

210

MHz

tPD

Q

1.1

1.65

ns

tPDSS

Q1.9

ns

tPD

CLK, CLK# (TSSOP)

Q

1.1

1.6

1.85

ns

tphl

RESET#

Q

3.5

ns

SYMBOL

VDD = 2.6V ±0.1V

UNITS

From

(Input)

To

(Output)

(VFQFN[MLF2])